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| smb135 ? summit microelectronics, inc. 2006 ? 757 north mary avenue ? sunnyvale ca 94085 ? phone 408 523-1000 ? fax 408 523-1266 http://www.summitmicro.com/ 2106 3.1 11/4/2008 1 programmable switch-mode, usb/ac input li+ battery charger with turbochar g e? mode* introduction ? programmable usb/ac li-ion battery charger ? turbocharge tm mode: 750ma output from 500ma usb ? high-efficiency current-mode pwm controller o 750khz to 1.25mhz switching frequency o 0% to 100% duty-cycle ? 4.35 to 6.5v input voltage range ? small 1.3 x 2.1 ucsp tm -15 package (0.4mm pitch) ? high-accuracy output voltage regulation: 1% ? low reverse leakage current ? digital programming of all major parameters via i 2 c interface (with several addresses) and non-volatile memory o battery voltage set point o pre-charge, fast charge, termination current o fast charge voltage threshold o temperature limits o automatic restart threshold ? status/fault indicator ? stability with ceramic capacitors ? wide range of protection features o thermal monitor o safety timers o current limit o input/output over-voltage lockout applications ? gsm handsets ? umts handsets ? portable media & gaming players ? digital camcorders/still cameras ? handheld gps/pdas the smb135 is a programmable singl e-cell lithium-ion/lithium-polymer battery charger for a variety of portable applications. the device provides a simple and efficient wa y to charge high-capacity li-ion batteries via a usb port or an ac adapter. unlike conventional devices, the smb135?s high-effici ency operation eliminates large internal temperature rise and locali zed hot spot in handheld equipment. summit?s proprietary turbocharge tm mode allows a 750ma charge current from a 500ma usb port, resulting to significantly reduced charge times. charge control includes qualificati on, trickle-charge, pre-charge, constant current/constant voltage, and termination/safety settings that are fully programmable via a serial i2c/smbus making the device truly a flexible solution. fast charge curr ent level (one or five unit loads) can be set via i 2 c or an input pin (usb500/100). an enable (en) pin is also provided for suspending usb c harging and allowing the device to work in parallel with ac charger, which may already be integrated into a pmic device. in this case, the smb135 does not allow current to flow back to the usb port. the smb135 offers a wide variety of features that protect the battery pack as well as the charger and i nput circuitry: over-current, under/over-voltage and thermal protection. ultra-precise, 1% accurate, kelvin-sensed adoc? technology allows accurate control of battery float voltage and improves battery capacity utilization. status can be monitored via the serial port for c harge state and fault conditions. in addition, one led driver output can be used to signal charge status or an under-/over-voltage condition. as a protection mechanism, when the junction temperature approaches approximately 110 c, the pwm switcher will start to cut back on the duty cycle, to reduce current. the smb135 is available in a space-saving 1.3mm x 2.1mm ucsp tm package with lead-free balls as well as in a lead-free 5x5 qfn-32 package, and is rated over the -30 c to +85 c temperature range. figure 1 ? applications block diagram featuring the smb135 programmable switch-mode battery charger. simplified applications drawing features & applications * patent pending usb controller d+ d- vdc gnd adc+ adc- in gnd stat r lim led 6.8uh smb135 senseh sensel 50-100m ? 10uf li-ion therm en out usb500/100 sda batt comp c comp r comp vddcap 1uf 4.7uf scl 500-700ma 4.35v-6.5v
smb135 summit microelectronics, inc 2106 3.1 11/4/2008 2 general description the smb135 is a fully programmable battery charger for single-cell li-ion and li-polymer battery packs. the device?s high-efficiency, switch-mode operation reduces heat dissipation and allows for higher current capability for a given package size. the smb135 provides four main charging phases: trickle-charge, pre-conditioning (pre-charge), constant current and constant voltage. the overall system accura cy of the smb135 is 1%, allowing for a higher capaci ty utilization versus other conventional solutions. when a battery or an external supply is inserted and the en (enable) input is asserted, the smb135 performs the pre-qualification checks before initiating a charging cycle. the input voltage needs to be higher than the uvlo threshold and the cell temperature needs to be within the temperature limits for the charging cycle to start. as soon as the input supply is removed, the smb135 enters a shutdown mode, thereby saving battery power. a programmable option also exists that allows the user to prevent battery charging until an i 2 c command has been issued. if the battery voltage is below 2.0v (trickle-charge to pre- charge threshold), the device will apply a trickle-charge current of 10ma (typical). this allows the smb135 to reset the protection circuit in the battery pack and bring the battery voltage to a higher level without compromising safety. once the battery voltage crosse s the 2.0v threshold, the smb135 enters the pre-charge mode. this mode replenishes deeply depleted cells and minimizes heat dissipation during the initial charge cycle. the preconditioning current is programmable, with the default value at c/10. if the battery voltage does not reach the preconditioning voltage level (programmable) within a specified amount of time (pre -charge timeout), the safety timer expires and the charge cycle is terminated. when the battery voltage reaches the pre-charge to fast- charge voltage level, the smb135 enters the constant current (fast charge) mode. the fast charge current level is programmable in two ways: a) via an external sense resistor and b) via the corresponding register. once the final float voltage (programmable) has been reached, the battery charger will enter a constant voltage mode in which the battery voltage is kept constant, allowing the charge current to gradually taper off. the constant-voltage charging m ode will continue until the charge current drops below the termination current threshold, or until the fast charge timer has expires. the termination current threshold is programmable from 25ma to 130ma in 15ma increments. after the charge cycle has terminated, the smb135 continues to monitor the batte ry voltage. if the battery voltage falls below the recharge threshold (typically 115mv below float voltage), the smb135 can automatically top-off the battery. a wide range of protection features is also included in the smb135. these include input and output over- voltage protection, battery missing detector and thermal monitor for continuous cell temperature monitoring and pre-qualification. the following charging parameters can be adjusted dynamically via the i2c interf ace, for optimizing battery management real-time. these parameters can also be programmed statically via a user-friendly gui interface: ? battery (float) voltage ? fast charge current ? pre-conditioning voltage threshold ? pre-conditioning charge current ? termination current ? safety charge timers ? temperature window the smb135 also offers three programmable pwm switching frequencies ranging from 750khz to 1250khz in 250khz increments. smb135 summit microelectronics, inc 2106 3.1 11/4/2008 3 figure 2 ? internal block diagram of the smb135 programmable switch-mode battery charger. z senseh batt in pwm control sensel internal temperature limit well control out comp therm z interface z eeprom z registers z charge control sda scl usb500/100 en z internal vdd regulator vddcap prog. cold limit prog. hot limit vddcap programmable current prog. float voltage z senseh batt in pwm control sensel internal temperature limit well control out comp therm z interface z eeprom z registers z charge control sda scl usb500/100 en z internal vdd regulator vddcap prog. cold limit prog. hot limit vddcap programmable current prog. float voltage internal block diagram smb135 summit microelectronics, inc 2106 3.1 11/4/2008 4 ball number (csp-15) pin number (qfn-32) pin name pin type pin description a1 1 batt i battery voltage sense ? connect di rectly to positive terminal of battery. b1 4 senseh i charge current sense ? connect to high-side of charge current sense resistor. c1 5 sensel i charge current sense ? connect to low-side of charge current sense resistor (allows for higher accuracy). d1 7 comp i primary compensation ? connect to r/c compensation network. e1 10 stat o status and fault indicator. a2 29 therm i/o battery thermistor sense. b2 27 vddcap pwr vdd bypass ? connect to vdd bypass capacitor with 1 f or greater capacitor. c2 3, 8, 18, 20, 22, 30, 32 agnd pwr analog ground ? connect to isolated pcb ground. d2 3, 8, 18, 20, 22, 30, 32 gnd pwr ground ? connect to isolated pcb ground. e2 12 in i usb (+4.35v to +5.5v) or adapt or input (+4.35v to +6.5v) ? bypass with a 1 f or greater capacitor. a3 25 en i enable input (active low) ? a logic low signal on this pin powers-up the device and allows a battery charge cycle to occur. a logic high signal on this pin forces in to a high- impedance, low-current state, and the internal vdd regulator is powered down. if unused, this pin should be tied to gnd. b3 24 usb500/100 i charge current regulation setting ? connect to logic high for 500ma or low for 100ma charge current setting. this charging current can be overridden by i2c but only for values less than 500ma and 100ma respectively. the actual charging values are (500-i offset ) ma and (100-i offset ) ma respectively, with i offset being the device?s total active current (note 1). when unused, this pin should be tied to vddcap or gnd (do not leave floating). c3 21 sda i/o i 2 c bus data. d3 19 scl i i 2 c bus clock. e3 14 out o charge current output ? connect to inductor. n/a 33 gnd pwr exposed metal (thermal) pad on bottom of smb135. the thermal pad of the smb135 package must be connected to the pcb gnd. n/a 2, 6, 9, 11, 13, 15, 16, 17, 23, 26, 28, 31 nc n/a package and pin descriptions smb135 summit microelectronics, inc 2106 3.1 11/4/2008 5 c1 c2 a2 b2 e1 a1 b1 d1 d2 e2 c3 b3 smb135 lead-free ucsp tm -15 1.3mm x 2.1mm a3 e3 d3 15-ball ultra csp tm bottom view package and pin descriptions (cont.) 1 smb135 5mm x 5mm qfn-32 2 3 13 therm 4 gnd 10 en 12 11 28 27 26 comp sda gnd 5 6 7 8 9 24 23 22 25 17 14 16 nc 15 18 20 21 gnd scl nc 19 gnd nc usb500/100 nc 32 31 30 29 nc nc nc gnd batt gnd senseh sensel gnd nc stat in nc out nc nc nc vdd_cap smb135 summit microelectronics, inc 2106 3.1 11/4/2008 6 recommended operating conditions absolute maximum ratings temperature un der bias ...................... -55 c to 155 c storage temper ature............................ -55 c to 125 c terminal voltage with respect to gnd: vin ................................................... -0.3v to +10v all others ........................................... -0.3v to +6v output short circ uit current ............................... 100ma lead solder temper ature ( 10 s).......................... 300 c junction temperature........ ...............?? .....?...150c hbm esd rating per jedec???????..?4000v mm esd rating per jedec???????.?.?200v cdm esd rating per jedec????????..1000v latch-up testing per jedec???..?....?? 100ma note ? the device is not guarant eed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditi ons outside those listed in the operational sections of the spec ification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. devices are esd sensitive. handling precautions are recommended. industrial temperature range ??? ? -30c to +85c vin ..........................................................+4.35v to +6.5v package thermal resistance ( ja ) ucsp tm -15??????????..? ???.....55c/w 5x5 qfn-32 (thermal pad connected to pcb).37.2c/w reliability characteristics data retention??????????..?..100 years endurance????????.???.100,000 cycles dc operating characteristics t a = -30 c to +85 c, v in = +5.0v, v float = +4.2v unless otherwise noted. all voltages are relative to gnd. symbol parameter conditions min typ max unit general v in input supply voltage v flt = 4.2v, i chg =100ma +4.35 +6.5 v v uvlo under-voltage lockout voltage v flt = 4.2v +3.5 v v uvlo-hys under-voltage lockout hysteresis v flt = 4.2v 10 mv v ovlo input over-voltage lockout voltage +7.0 v v bov battery over-voltage lockout voltage v flt +0.1 v v ashdn automatic shutdown threshold voltage v in ? v batt 130 mv i dd-active active supply current pwm not switching 0.8 4 ma i offset active supply current pwm switching 5 ma i dd-shdn shutdown supply current input voltage present 7 20 a i lk reverse leakage current v in < v batt (no adapter), t=0 o c to +70 o c 2 a t reg thermal regulation temperature 110 o c smb135 summit microelectronics, inc 2106 3.1 11/4/2008 7 dc operating characteristics (continued) t a = -30 c to +85 c, v in = +5.0v, v float = +4.2v unless otherwise noted. a ll voltages are relative to gnd. symbol parameter conditions min typ max unit switch-mode controller r rdson fet on-resistance v in = 5.0v 550 m ? i limit current limit f osc =1.25mhz, v batt =3.0v 1000 ma maximum 100 % d.c. duty cycle minimum 0 % logic inputs/output v il input low level all inputs except en 600 mv v ih input high level all inputs except en 1.4 v v ilen input low level 400 mv v ihen input high level 1.2 v v ol sda/stat output low level i sink =3ma 300 mv i bias input bias current 1 a i sink stat sink current 5 ma battery charger v sense constant current sense voltage fast-charge mode, maximum voltage across sense resistor 52.5 mv v tricklechg trickle-charge to pre-charge voltage threshold 2.0 v i tricklechg trickle-charge current 10 ma v prechg pre-charge to fast-charge voltage threshold 100mv steps 2.400 3.100 v i prechg nominal pre-charge current 12.5ma steps, r sense = 0.1 ? 25 212.5 ma ? i prechg pre-charge current tolerance i prechg = 100ma, r sense = 0.1 ? , t=0 o c to +70 o c 75 100 125 ma i fchg nominal fast charge current 16 steps, r sense = 0.1 ? 47.5 525 ma usb500/100=vin, note 1 495 525 555 ma i chg nominal charge current usb500/100=gnd, note 1 75 100 125 ma ? i chg fast charge current tolerance i fchg = 525ma, r sense = 0.1 ? , t=0 o c to +70 o c 495 525 555 ma v flt float voltage range 20mv steps 4.020 4.620 v ? v flt float voltage tolerance t=+10 o c to +50 o c, v flt = 4.2v -1 +1 % i term charge termination current 15ma steps, r sense = 0.1 ? 25 130 ma ? i term termination current tolerance i term = 55ma, r sense = 0.1 ? , t=0 o c to +70 o c 25 85 ma note 1: the actual charging current always equals the nom inal values given in the register tables minus i offset , where i offset is the device?s total active current. the 525ma nominal value shown here is with the hex value f in register h00[7:4]. for usb1, the nominal value is the lower of the one selected in the register and 100ma. note 2: voltage, current and frequency accuracies are only guaran teed for factory-programmed settings. changing any of these pa rameters from the values reflected in the customer specific csir code w ill result in inaccuracies exceeding those specified above. note 3: the smb135 device is not intended to function as a batte ry pack protector. battery packs used in conjunction with this device need to provide adequate internal protection and to comply with the corresponding battery pack specifications. smb135 summit microelectronics, inc 2106 3.1 11/4/2008 8 dc operating characteristics (continued) t a = -30 c to +85 c, v in = +5.0v, v float = +4.2v unless otherwise noted. a ll voltages are relative to gnd. symbol parameter conditions min typ max unit battery charger v rech recharge threshold voltage 115 mv cmr common mode range current sense amplifier, note 4 2 v batt v t hi charge cutoff temp (high) adjustable, conditions per typical application 30 65 o c t lo charge cutoff temp (low) adjustable, conditions per typical application -20 15 o c note 4: guaranteed by design. ac operating characteristics t a = -30 c to +85 c, v in = +5.0v, v float = +4.2v unless otherwise noted. a ll voltages are relative to gnd. symbol description conditions min typ max unit oscillator f osc frequency range 250khz steps (3 settings) 750 1250 khz ? f osc frequency accuracy f osc =1.25mhz (default), t=0 o c to +70 o c 1.125 1.250 1.375 mhz t start start-up time note 5 20 ms disabled 0 msec t glitch glitch filter enabled 250 msec short 0 1 msec t holdoff hold-off time long 256 msec t fcto = 350min t fcto = 699min t fcto fast-charge timeout t fcto = 1398min -15 t fcto +15 % t pcto = 44min t pcto = 87min t pcto pre-charge timeout t pcto = 175min -15 t pcto +15 % note 5: this is the time it takes for the device to be ready for i2c communication or chargi ng after power-up (including coming out of shutdown). when charging is enabled, actual charging begins after the hold-off timer has expired. smb135 summit microelectronics, inc 2106 3.1 11/4/2008 9 figure 3 ? typical smb135 charging algorithm ) charging algorithm (500ma) charge algorithm (cc-cv) vs. time 1.50 2.00 2.50 3.00 3.50 4.00 4.50 time battery voltage (v) 0.001 0.01 0.1 1 log current (a) battery voltage charge current input current trickle charge vbat<2.00v itrickle = 10ma pre-charge vbat smb135 summit microelectronics, inc 2106 3.1 11/4/2008 11 efficiency graphs figure 6: smb135 qfn efficiency vs voltage v in =5v, i fchg =500ma, l=6.8uh (tdk:vlf4012), t a =25c 75 80 85 90 95 100 3 3.2 3.4 3.6 3.8 4 4.2 v batt (v) efficiency (%) 1.25mhz 1mhz 750khz figure 5: smb135 qfn efficiency vs voltage v in =5v, i fchg =500ma, f=1.25mhz, t a =25c 75 80 85 90 95 100 3 3.2 3.4 3.6 3.8 4 4.2 v batt (v) efficiency (%) taiyo y 4.7uh tdk 6.8uh smb135 summit microelectronics, inc 2106 3.1 11/4/2008 12 output current graph figure 7: output current vs. battery voltage v in =5v, i fchg =1000ma, r sense =50mohm, f=1.25mhz, v float =4.2v,t a =25c 700 800 900 1000 1100 3.00 3.50 4.00 4.50 v batt (v) i batt (ma) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 13 applications information device operation the smb135 is a fully programmable battery charger for single-cell li-ion and li-polymer battery packs. the device?s high-efficiency, switch-mode operation reduces heat dissipation and allows for higher current capability for a given package size. the smb135 provides four main chargi ng phases: trickle-charge, pre-conditioning (pre-charge) , constant (fast-charge) current and constant voltage. the overall system accuracy of the smb135 is 1%, allowing for a higher capacity utilization versus other conventional solutions. furthermore, the main battery charging parameters are programmable, allowing for high design flexibility and sophisticated battery management. power supply the smb135 can be powered from an input voltage between +4.35 and +6.5 volts applied between the in pin and ground. the voltage on the in pin is monitored by under-voltage (uvlo) and over-voltage lockout (ovlo) circuits, which prevent the charger from turning on when the voltage at this node is less than the uvlo threshold (+3.5v), or grea ter than the ovlo threshold (+7.0v). the in pin also supplies an internal +2.5v vdd regulator, filtered by an external capacitor attached between the vddcap pin and ground; this filtered voltage is then used as an internal vdd supply. when the input supply is removed, the smb135 enters a low-power shutdown mode, exhibiting a very low discharge leakage current (2a), thereby extending battery life. pre-qualification mode when an external wall adaptor or a usb cable is connected, the smb135 performs a series of pre- qualification tests before initia ting the first charge cycle. the input voltage level needs to be higher than the uvlo threshold, lower than the ovlo threshold and 130mv greater than the battery voltage; the enable input needs to be asserted or the appropriate i2c command needs to be asserted; and the cell temperature needs to be within the specified temperature limits for the charging cycle to start. the pre-qualification parameters are continuously monitored and charge cycle is suspended when one of them is outside the limits. trickle-charge mode once all pre-qualification c onditions are met, the device checks the battery voltage to decide if trickle-charging is required (figure 3). if the battery voltage is below approximately 2.0v, a charging current of 10ma (typical) is applied on the ba ttery cell. this allows the smb135 to reset the protection circuit in the battery pack and bring the battery voltage to a higher level without compromising safety. pre-charge mode once the battery voltage crosses the 2.0v level, the smb135 pre-charges the battery to safely charge the deeply discharged cells (figure 3). the pre-charge (pre-conditioning) current is programmable from 25ma to 212.5ma in 12.5ma steps, assuming a sense resistor of 100m ? (register 00h). the smb135 remains in this mode until the battery voltage reaches the pre-charge to fast-charge voltage threshold (programmable from +2.4v to +3.1v in 100mv steps). if the pre-charge to fast-charge voltage threshold is not exceeded before the pre-charge timer expires, the charge cycle is terminated and a corresponding timeout fault signal is asserted (?pre-charge timeout? in register 36h). constant current mode when the battery voltage exceeds the pre-charge to fast-charge voltage threshol d, the device enters the constant current (fast charge) mode. during this mode, the fast charge current level is set by either the usb500/100 input (see below) or the corresponding register. the fast charge cu rrent is programmable from 47.5ma to 525ma (16 steps), assuming a sense resistor of 100m ? (register 00h). constant voltage mode when the battery voltage reaches the pre-defined float voltage, the fast-charge current starts diminishing. the float voltage is programmable from +4.00v to +4.62v in 20mv steps and is 1% accurate over the 0 c to +70 c temperature range. the higher float voltage settings of the smb135 enable the charging of modern battery packs with a required float voltage of 4.3v, 4.4v, and 4.5v. furthermore, the abilit y to dynamically adjust the float voltage allows the impl ementation of sophisticated battery charging and control algorithms. charge completion the charge cycle is considered complete when the charge current reaches the programmed termination current threshold. the termination current is programmable from 25ma to 130ma in 15ma steps, assuming a sense resistor of 100m ? (register 01h). if the termination current threshold is not met before the fast-charge timer expires, the charge cycle is terminated and a corresponding timeout fault signal is asserted (?fast-charge tim eout? in register 36h). smb135 summit microelectronics, inc 2106 3.1 11/4/2008 14 en (enable) en is a logic input pin (active low) for enabling/disabling the device and/or restarting a charge cycle. when en is held at a high logic level, in goes into a high impedance state, the internal vdd regulator is powered down, no communication can occur over the i2c bus, and no charge cycles may proceed. en must be held low in order to get any functionality out of the device. if unused, this pin should be tied to gnd. charge enable the initiation of a charge cycle is controlled via the state of the volatile command register (register 31, bit 4) and register 0f bit 7. bit 0f[7] controls the polarity of the command bit 31[4]; if 0f[7] is low, then a 0 at 31[4] will cause a charge cycle to start. since the volatile register always powers-up to all 0?s, then 0f[7] determines whether a charge cycle may begin on power up, or whether an i2c command must be issued to initiate charging. usb500/100 usb500/100 is a logic input that allows the user to select a maximum fast charge current of 100ma or 500ma. when a logic high signal is applied on this pin, the charge current level may be as high as 500ma. when a logic low signal is applied on this input, the charge current level is limited to 100ma. in all cases, a lower register value setting will impose an overriding current limit. when the usb500/100 input is not used, this pin should be tied to vddcap or gnd (do not leave floating). the usb500/100 functionality can also be controlled over the i2c interface (ignoring the state of the pin), allowing for full software control of charge current levels. this function is accomplished via register 31 bit 3, when register 7 bit 0 is programmed high. automatic battery recharge the smb135 allows the battery to be automatically recharged (topped off) when the battery voltage falls by a value of v rech (115mv typical) below the programmed float voltage. provided that the input power supply is still present, charging remains enabled and all the pre-qualification parameters are still met, a new charging cycle w ill be initiated. this ensures that the battery capacity remains high, without the need to manually re-start a chargi ng cycle. the automatic battery recharging can be di sabled if not required by the application (register 03h). safety timers the integrated safety timers provide protection in case of a defective battery pack. the pre-charge timer starts after the pre-qualification check is completed and resets when the transition to the constant current mode happens. at that point, the fast charge timer is initiated. the fast charge timer expires and charge cycle is terminated if the termination current level is not reached within the pre-determined duration. each safety timer has three programmable timeout periods, which eliminates the need for external timing capacitors and allows for maximum design flexibility. in addition, each timer can be disabled by the appropriate bit selection in register 05h. thermal monitor a temperature sensing i/o (therm) is provided to prevent excessive battery temperatures during charging. the battery temperature is measured by sensing the voltage between the therm pin and ground. the voltage is created by injecting a current into the parallel combination of negative temperature coefficient (ntc) thermistor and a resistor. this voltage is then compared to two predetermined voltages representing the maximum and minimum temperature settings of the battery. the purpose of the resistor in parallel to the nt c thermistor is to linearize the resistance of the thermistor. the table below, shows the 1% resistor that should be placed in parallel with the corresponding thermistor. if the temperature limits are exceeded, battery charging will be suspended until the temperature level has fallen within the safe operating range. the over-temperature limit is programmable from 30 c to 65 c, and the under-temperature limit is programmable from ? 20 c to 15 c, each in 5 c increments using register 04h. in addition, the user can easily select the required bias current, based on the value of the negative temperature coefficient (ntc) thermistor located in the battery pack: 10k, 25k, 100k (register 04h). disabling the thermal monitor is also possible by selecting the appropriate bits in register 04h. as the temperature changes, the resistance of the thermistor changes creating a voltage proportional to temperature. the temperature coefficient or beta ( ) of the thermistor must be as close to 4400 as possible to achieve the maximum temperature accuracy. ntc thermistor resistance 10k 24.9k 25k 61.9k 100k 249k table: ntc values and associated parallel resistances. applications information (continued) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 15 frequency selection the smb135 can operate at three different switching frequencies (750khz, 1mhz, 1.25mhz), which are selectable via an i 2 c command (register 08h). stat output the stat is an open-drain output that indicates battery charge status or an inpu t under-voltage/over-voltage (uv/ov) condition. the type of indication can be selected via the corresponding bit in register 07h. stat has two modes of oper ation, as determined by register 05h[7]: in mode 0, stat is asserted low whenever the battery is charging and de - asserted at all other times; in mode 1, stat is de-asserted when the charger is disabled, blinks during charging, and remains continuously asserted when the charge cycle has completed. a pull-up resistor should be applied on this pin for interfacing to a microcontroller or other logic ic. programmable battery charging a unique feature of the smb135 is the ability to modify all of the important charger parameters via internally programmable eeprom, found in registers 00-07. once the device has been configured correctly, the eeprom may be locked, pr eventing any further changes. additionally, these registers may also be configured so that they may be updated in ram (volatile), even if the under lying eeprom is locked. this feature is useful if it is desired to actively manage the charging profile without making changes to the non- volatile defaults. use regi ster 0e to control locking and volatile access. before writing to registers 00-07 in a volatile manner, register 31[7] must first be set high. fault and status indicators a large number of battery charging conditions and parameters are monitored and corresponding fault and status indications are available to the user via the i 2 c compatible registers. these include the following: ? charging status ? safety timer timeout ? over-temperature alarm ? under-temperature alarm ? over-voltage alarm ? under-voltage alarm ? missing battery detection glitch filter the smb135 features a glitch filter to ensure that short violations in the uv or ov settings will not result in a fault-triggered action. the glitch filter is user- programmable (register 05h) and may be set to 0msec (glitch filer disabled) or to 250msec. enabling the glitch filter will delay ?automatic recharge? and ?current termination? by 250msec. hold-off timer the smb135 features a hold-off timer that defines the amount of time from enabling the charger output until current begins flowing (trickle charge is excluded from this condition). two choices (short & long) are available: <1msec or 256msec. the short timer is asynchronous and could be any value between 0msec and 1msec. internal thermal protection when the die temperatur e of the smb135 reaches approximately 110c, the pwm switcher will cut back on the duty cycle to reduce current and prevent further die heating. this internal thermal protection circuit helps to improve device (and consequently, system) reliability. applications information (continued) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 16 external components (figure 9) input and output capacitors the input capacitor needs to absorb all reflected input switching ripple current generated by the smb135 device during chargi ng, so that no rippl e current will be seen on the input supply. the rms value of input ripple current in buck type charger is given by, vin vbat vin vbat ibat irms ) ( ? ? = . a 4.7uf ceramic capacitor, x5r or x7r rated, with the 0603 size and low esr sufficiently accommodates the above rms current. the output capacitor needs to ensure stability of the charger and low output ripple voltage. a 10uf ceramic capacitor, x5r or x7r rated, with the 0603 size and low esr can make operations of the smb135 device stable and absorb all ac portion of the inductor switching ripple current, since the rms value of the output ripple current is much smaller than that of the input ripple current. inductor the inductor in a buck type charger should be selected so that all its form-factor, cost, switching ripple and efficiency conform to the system requirement, or constitute the best compromise. small dimensions, higher inductance value usually suggests higher dcr value. high dcr generates high conduction loss. lower inductance value has less dcr but creates larger switching ripple current, which produces higher ac loss in the magnetic core and the windings. setting the peak-to-peak ripple current approximately 30% of the maximum charge current is a commonly used method. thus, fs vin vbat l vbat vin i l ? ? ? = ? max max , and, max % 30 ibat i l ? = ? , where, l is inductance, fs is the switching frequency. diode the rectifying diode circulat es the inductor current when the internal top fet is turned off. this causes the forward voltage drop across the diode. thus the diode power loss is, vin vbat vin ibat v p fd diode loss ? ? ? = _ . minimize the diode power loss by choosing a low forward voltage diode. the reverse blocking voltage rating that is considerably higher than the input voltage withstands any spike voltage that might appear across the diode. be cautious of the reverse leakage current that constantly bleeds a small power out the battery cells when the battery cells aren?t charged. board layout recommendations the smb135 only requires an inductor, a rectifying diode, an input capacitor, an output capacitor, a sense resistor and some bypass components, the high side fet is internal (figures 9, 10 and 11, table 1). place an input capacitor close to the ic. place an inductor, a rectifying diode, and an output capacitor close to each other. place a vdd cap, a comp capacitor and a comp resistor close to the pins. pour sufficiently large copper shapes on both sides of the sense resistor, toward the output capacitor and toward the battery cells. pour large copper shapes on the ?in?, ?out? and ?gnd? nodes as well. if it is necessary to route from these nodes to the other side of the board, place enough number of vias. accuracy of current measurements and therefor e accuracy of charge current control are at maximum only if both the senseh trace and the sensel trace are directly connected to each side of the resistor pads without contacting any shapes on their ways. make the two routes a differential pair if possible. internal ground planes and power planes quickly sink heat generated by the smb135, the rectifyi ng diode, and the inductor, furthermore reduce noise concern for the ic by providing shielding. applications information (continued) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 17 figure 8 ? functional flow chart. applications information (continued) standby mode (pause charge) vin > vbat+130mv ? (always monitored) no por yes vbat smb135 summit microelectronics, inc 2106 3.1 11/4/2008 18 figure 9 ? typical applications schematic. the usb device has internal pull up resistors for sda and scl. applications information (continued) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 19 table 1: recommended bill of material. item description vendor / part number qty ref. des. resistors 1 15kohm, 1%, 0402 vis hay# crcw04021502f 1 r3 2 10kohm, 1%, 0402 vis hay# crcw04021002f 3 r4, r12, r13 3 100mohm, 1%, 0402, 1/6w susumu# rp1005s-r10-f-c 1 r5 4 24.9kohm, 1%, 0402 vi shay# crcw04022492f 1 r11 5 10kohm, thermistor, 0402 tdk# ntcg103jf103ft 1 rt1 capacitors 6 10uf, 0603, x5r, 6.3v, ceramic tdk# c1608x5r0j106m 1 c5 7 4.7uf, 0805, x5r, 16v, ceramic murata# grm40x5r475k16d520 1 c1 8 1uf, 0402, x5r, 10v, ceramic panasonic# ecj-0eb1a105m 1 c2 9 2200pf, 0402, x5r, 25v, cera mic vishay# vj0402y222kxxa 1 c3 10 0.1uf, 0402, x7r, 16v, ceramic kemet# c0402c104k4ractu 3 c7, c8, c9 semiconductors 11 rb551v-30, sod-323, 30v, 0.5a, 0.47vf rohm# rb551v-30te-17 1 d1 12 led, red, smd, 0805 lumex# sml-lxt0805srw 1 d2 13 cypress cy7c63001a usb to i 2 c micro delcom engineering #802200 1 u1 14 crystal oscillator, smt, 6mhz digikey# 300-6112-1-nd 1 y1 15 smb135e summit microelectronics 1 u2 magnetics 6.8uh, 0.96a (saturation), 0.97a (dc) tdk# vlf4012at-6r8mr96 1 l1 16 4.7uh, 1.02a (saturation), 1.04a (dc) taiyo yuden # nr3015t4r7m 1 l1 (alternate) hardware 17 connector receptacle mini usb type b 2.0 digi-key, h2960ct-nd hirose electric usa ux60-mb- 5s8 h2960ct 1 j1 applications information (continued) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 20 figure 10 ? example layout. the top side layout provides space (u2) for an smb135 device packaged in a leadless qfn package (not to scale). figure 11 ? example layout. the bottom side layout provides space (u3) for a smb135e device packaged in a csp package. layout ? bottom side layout ? top side smb135 summit microelectronics, inc 2106 3.1 11/4/2008 21 development hardware & software the smx3202 system consists of a usb programming dongle, cable and windows tm gui software. it can be ordered on the website or fr om a local representative. the latest revisions of all software and an application brief describing the smx3202 is available from the website ( www.summitmicro.com ). the smx3202 programming dongle/cable interfaces directly between a pc?s usb port and the target application. the device is t hen configured on-screen via an intuitive graphical user interface employing drop- down menus. the windows gui software will generate the data and send it in i 2 c serial bus format so that it can be directly downloaded to the smb135 via the programming dongle and cable. an example of the connection interface is shown in figure 12. when design prototyping is complete, the software can generate a hex data file that should be transmitted to summit for approval. summit will then assign a unique customer id to the hex code and program production devices before the final electrical test operations. this will ensure proper devic e operation in the end application. pin 9, 5.0v pin 7, 10v pin 5, reserved pin 3, gnd pin 1, gnd pin 6, mr# pin 4, sda pin 2, scl pin 8, en pin 10, usb500/100 top view of straight 0.1" x 0.1" closed-side connector. smx3202 interface connector. 9 7 5 3 1 10 8 6 4 2 sda scl in gnd 0.1 f en usb500/100 smb135 figure 12 ? smx3202 programmer i 2 c serial bus connections to program the smb135. only sda and scl connections are necessary for programming purposes, the other 2 pins are control options provided by the smx3202 and windows gui, see pin descriptions smb135 summit microelectronics, inc 2106 3.1 11/4/2008 22 i 2 c programming information serial interface access to the configuration registers, command and status registers is carried out over an industry standard 2-wire serial interface (i 2 c). sda is a bi- directional data line and scl is a clock input (figure 4). data is clocked in on the rising edge of scl and clocked out on the falling edge of scl. all data transfers begin with the msb. during data transfers, sda must remain stable while scl is high. data is transferred in 8-bit packets with an intervening clock period in which an acknowledge is provided by the device receiving data. the scl high period (t high ) is used for generating start and stop conditions that precede and end most transactions on the serial bus. a high-to-low transition of sda while scl is high is considered a start condition while a low-to-high transition of sda while scl is high is considered a stop condition. the interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. the address byte is comprised of a 7-bit device type identifier (slave address). the remaining bit indicates either a read or a write operation. refer to table 1 for a description of the address bytes used by the smb135. the device type identifier for the configuration registers and the command and status registers are accessible with the same slave address. the slave address can be can be progra mmed to any seven bit number 0000000 bin through 1111111 bin . table 2. write writing to a configuration r egister is illustrated in figures 13 and 14. a start condition followed by the slave address byte is provided by the host; the smb135 responds with an acknowledge; the host then responds by sending the me mory address pointer or configuration register ad dress pointer; the smb135 responds with an acknowledge; the host then clocks in one byte of data. for configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. after the last byte is clocked in and the host receives an acknowledge, a stop condition must be issued to initiate the nonvolatile write operation. read the address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the smb135. this is accomplished by issuing a dummy write command, which is a write command that is not followed by a stop condition. a dummy write command sets the address from which data is read. after the dummy write command is issued, a start command follo wed by the address byte is sent from the host. the host then waits for an acknowledge and then begins clocking data out of the slave device. the first byte read is data from the address pointer set during the dummy write command. additional bytes can be clocked out of consecutive addresses with the host providing an acknowledge after each byte. after the data is read from the desired registers, the read operation is terminated by the host holding sda high during the acknowledge clock cycle and then issuing a stop condition. refer to figure 15 for an illustration of the read sequence. configuration registers writing and reading the configuration registers is shown in figures 13, 14 and 15. a description of the configuration registers is shown in table 3 through table 12. graphical user interface (gui) device configuration ut ilizing the windows based smb135 graphical user interface (gui) is highly recommended. the software is available from the summit website ( www.summitmicro.com ). using the gui in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. a programming dongle (smx3202) is available from summit to communicate with the smb135. the dongle connects directly to the usb port of a pc and programs the device through a cable using the i 2 c bus protocol. see figure 12 and the smx3202 data sheet. slave address register type any configuration registers are located in 00 hex thru 05 hex , 08 hex and 0f hex table 2 ? address bytes used by the smb135. smb135 summit microelectronics, inc 2106 3.1 11/4/2008 23 s t a r t bus address w a c k master slave a c k configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p data a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 13 ? configuration register byte write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p master master slave slave a c k data (16) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (2) a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 14 ? configuration register page write s t a r t bus address w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s t o p n a c k master master slave slave a c k data (n) configuration register address c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 s t a r t r a c k bus address a c k d 7 d 6 d 5 d 2 d 1 d 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data (1) a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 a 2 a 1 a 0 s a 3 s a 2 s a 1 s a 0 figure 15 ? configuration register read i 2 c programming information (continued) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 24 the following tables (tables 3 to 15) describe the user -programmable registers of the smb135 programmable battery charger. locations 00-0f ar e non-volatile, eeprom register s; however, registers 00-07, which contain the battery charging parameters, may also be configured to be programmabl e in ram. locations 31-3f contain volatile status and command registers. to lock all of the configuration regist ers, set 0e[2]=1; please note that this operation cannot be undone . to allow volatile access to locations 00-07, set 0e [0]=1; then after every power- on, 31[7] must also be set high. it is prohibited to write to any location, no t specifically mentioned in the tables below 7 . default register settings are in bold . table 3 ? charge current ? 8-bit (address: 00h) ? non-volatile & volatile (mirror) fast charge current bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r sense =100m ? r sense =50m ? 0 0 0 0 x x x x 47.5ma 95ma 0 0 0 1 x x x x 62.5ma 125ma 0 0 1 0 x x x x 65.0ma 130ma 0 0 1 1 x x x x 67.5ma 135ma 0 1 0 0 x x x x 195ma 390ma 0 1 0 1 x x x x 225ma 450ma 0 1 1 0 x x x x 255ma 510ma 0 1 1 1 x x x x 285ma 570ma 1 0 0 0 x x x x 315ma 630ma 1 0 0 1 x x x x 345ma 690ma 1 0 1 0 x x x x 375ma 750ma 1 0 1 1 x x x x 405ma 810ma 1 1 0 0 x x x x 435ma 870ma 1 1 0 1 x x x x 465ma 930ma 1 1 1 0 x x x x 495ma 990ma 1 1 1 1 x x x x 525ma 1050ma pre-charge current bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r sense =100m ? r sense =50m ? x x x x 0 0 0 0 25ma 50ma x x x x 0 0 0 1 37.5ma 75ma x x x x 0 0 1 0 50ma 100ma x x x x 0 0 1 1 62.5ma 125ma x x x x 0 1 0 0 75ma 150ma x x x x 0 1 0 1 87.5ma 175ma x x x x 0 1 1 0 100ma 200ma x x x x 0 1 1 1 112.5ma 225ma x x x x 1 0 0 0 125ma 250ma x x x x 1 0 0 1 137.5ma 275ma x x x x 1 0 1 0 150ma 300ma x x x x 1 0 1 1 162.5ma 325ma x x x x 1 1 0 0 175ma 350ma x x x x 1 1 0 1 187.5ma 375ma x x x x 1 1 1 0 200ma 400ma x x x x 1 1 1 1 212.5ma 425ma note 7: never write to reserved bits. note 8: charge current can be limited by internal current limit under certain conditions . configuration registers smb135 summit microelectronics, inc 2106 3.1 11/4/2008 25 table 4 ? termination current ? 8-bit (address: 01h) ? non-volatile & volatile (mirror) termination current bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r sense =100m ? r sense =50m ? x x x x x 0 0 0 25ma 50ma x x x x x 0 0 1 40ma 80ma x x x x x 0 1 0 55ma 110ma x x x x x 0 1 1 70ma 140ma x x x x x 1 0 0 85ma 170ma x x x x x 1 0 1 100ma 200ma x x x x x 1 1 0 115ma 230ma x x x x x 1 1 1 130ma 260ma note 7: never write to reserved bits. configuration registers ( cont. ) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 26 table 5 ? float voltage ? 8-bit (address: 02h) ? non-volatile & volatile (mirror) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 float voltage x x x 0 0 0 0 0 3.850v x x x 0 0 0 0 1 4.020v x x x 0 0 0 1 0 4.040v x x x 0 0 0 1 1 4.060v x x x 0 0 1 0 0 4.080v x x x 0 0 1 0 1 4.100v x x x 0 0 1 1 0 4.120v x x x 0 0 1 1 1 4.140v x x x 0 1 0 0 0 4.160v x x x 0 1 0 0 1 4.180v x x x 0 1 0 1 0 4.200v x x x 0 1 0 1 1 4.220v x x x 0 1 1 0 0 4.240v x x x 0 1 1 0 1 4.260v x x x 0 1 1 1 0 4.280v x x x 0 1 1 1 1 4.300v x x x 1 0 0 0 0 4.320v x x x 1 0 0 0 1 4.340v x x x 1 0 0 1 0 4.360v x x x 1 0 0 1 1 4.380v x x x 1 0 1 0 0 4.400v x x x 1 0 1 0 1 4.420v x x x 1 0 1 1 0 4.440v x x x 1 0 1 1 1 4.460v x x x 1 1 0 0 0 4.480v x x x 1 1 0 0 1 4.500v x x x 1 1 0 1 0 4.520v x x x 1 1 0 1 1 4.540v x x x 1 1 1 0 0 4.560v x x x 1 1 1 0 1 4.580v x x x 1 1 1 1 0 4.600v x x x 1 1 1 1 1 4.620v note 7: never write to reserved bits. configuration registers ( cont. ) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 27 table 6 ? other charging parameters ? 8-bit (address: 03h) ? non-volatile & volatile (mirror) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 automatic recharge 0 x x x x x x x enabled 1 x x x x x x x disabled bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 current termination x 0 x x x x x x enabled x 1 x x x x x x disabled bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pre-charge to fast-charge voltage threshold x x 0 0 0 x x x 2.4v x x 0 0 1 x x x 2.5v x x 0 1 0 x x x 2.6v x x 0 1 1 x x x 2.7v x x 1 0 0 x x x 2.8v x x 1 0 1 x x x 2.9v x x 1 1 0 x x x 3.0v x x 1 1 1 x x x 3.1v bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hold-off timer x x x x x x 0 x <1msec (short) x x x x x x 1 x 256msec (long) table 7 ? cell temperature monitor ? 8-bit (addr ess: 04h) ? non-volatile & volatile (mirror) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 thermistor current 0 0 x x x x x x 100 a (10k ntc) 0 1 x x x x x x 40 a (25k ntc) 1 0 x x x x x x 10 a (100k ntc) 1 1 x x x x x x 0 a (disabled) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 low temperature alarm trip point x x 0 0 0 x x x -20 c x x 0 0 1 x x x -15 c x x 0 1 0 x x x -10 c x x 0 1 1 x x x -5 c x x 1 0 0 x x x 0 c x x 1 0 1 x x x +5 c x x 1 1 0 x x x +10 c x x 1 1 1 x x x +15 c bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 high temperature alarm trip point x x x x x 0 0 0 +30 c x x x x x 0 0 1 +35 c x x x x x 0 1 0 +40 c x x x x x 0 1 1 +45 c x x x x x 1 0 0 +50 c x x x x x 1 0 1 +55 c x x x x x 1 1 0 +60 c x x x x x 1 1 1 +65 c note 7: never write to reserved bits. configuration registers ( cont. ) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 28 table 8 ? battery charging control ? 8-bit (address: 05h) ? non-volatile & volatile (mirror) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 status output 0 x x x x x x x stat is active low while charging, active high all other times 1 x x x x x x x stat blinks while charging, is active low when finished, active high when disabled bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 glitch filter x x 0 x x x x x glitch filter enabled x x 1 x x x x x glitch filter disabled bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fast-charge timeout x x x x 0 0 x x 350 min x x x x 0 1 x x 699 min x x x x 1 0 x x 1398 min x x x x 1 1 x x disabled bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pre-charge timeout x x x x x x 0 0 44 min x x x x x x 0 1 87 min x x x x x x 1 0 175 min x x x x x x 1 1 disabled table 9 ? stat and usb500/100 settings ? 8-bit (address: 07h) ? non-volatile bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 stat output indicator x x x x x 0 x x battery charge status x x x x x 1 x x input over-voltage or input under-voltage bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 battery over-voltage behavior x x x x x x 0 x charger is not shutdown x x x x x x 1 x charger is shutdown bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb500/100 control x x x x x x x 0 usb500/100 input pin x x x x x x x 1 usb500/100 register (address 31h) table 10 ? frequency selection ? 8-bit (address: 08h) ? non-volatile bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 switching frequency 0 0 x x x x x x 750khz 0 1 x x x x x x 1000khz 1 0 x x x x x x 1250khz 1 1 x x x x x x 1250khz note 7: never write to reserved bits. configuration registers ( cont. ) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 29 table 11 ? configuration and user memory lock ? 8-bit (address: 0eh) ? non-volatile bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 configuration lock x x x x x 0 x x unlocked ? user can write to non-volatile configuration bits x x x x x 1 x x locked ? user cannot write to non-volatile configuration bits bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 user-memory lock x x x x x x 0 x unlocked ? user can write to general purpose ee bits (h20-h2f) x x x x x x 1 x locked ? user cannot write to general purpose ee bits (h20-h2f) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 volatile writes permission x x x x x x x 0 do not allow volatile writes to registers h00- h07 x x x x x x x 1 allow volatile writes to registers h00-h07 (even if h0e[2]=1) table 12 ? en polarity & i 2 c bus/slave address ? 8-bit (address: 0fh) ? non-volatile bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en (enable) polarity (register 31[4]) 0 x x x x x x x active low 1 x x x x x x x active high bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c bus address x 0 0 0 x x x x 000 x 0 0 1 x x x x 001 x 0 1 0 x x x x 010 x 0 1 1 x x x x 011 x 1 0 0 x x x x 100 x 1 0 1 x x x x 101 x 1 1 0 x x x x 110 x 1 1 1 x x x x 111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c slave address x x x x 0 0 0 0 0000 x x x x 0 0 0 1 0001 x x x x 0 0 1 0 0010 x x x x 0 0 1 1 0011 x x x x 0 1 0 0 0100 x x x x 0 1 0 1 0101 x x x x 0 1 1 0 0110 x x x x 0 1 1 1 0111 x x x x 1 0 0 0 1000 x x x x 1 0 0 1 1001 x x x x 1 0 1 0 1010 x x x x 1 0 1 1 1011 x x x x 1 1 0 0 1100 x x x x 1 1 0 1 1101 x x x x 1 1 1 0 1110 x x x x 1 1 1 1 1111 note 7: never write to reserved bits. configuration registers ( cont. ) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 30 table 13 ? volatile configuration & charger enable ? 8-bit (address: 31h) ? volatile bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 volatile configuration 0 x x x x x x x volatile writes to h00-h07 are disabled 1 x x x x x x x volatile writes to h00-h07 are enabled (if cfg h0e[0]=1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 charger enable x x x 0 x x x x enabled if 0f[7]=0; disabled if 0f[7]=1 x x x 1 x x x x disabled if 0f[7]=0; enabled if 0f[7]=1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb500/100 select (this bit only has an effect when cfg 07[0]=1) x x x x 0 x x x usb 100ma current level x x x x 1 x x x usb 500ma current level table 14 ? battery status register a ? 8-bit (address: 36h) ? volatile (read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 charging status 1 x x x x x x x charger has completed at least 1 successful charge since being enabled x 1 x x x x x x charger has completed at least 1 re-charge cycle since being enabled bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 timeout status x x 0 0 x x x x no timeouts have occurred x x 0 1 x x x x pre-charge timeout x x 1 0 x x x x fast-charge timeout bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 temperature fault x x x x 1 x x x charger paused ? temperature fault bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 charging status x x x x x 0 0 x idle x x x x x 0 1 x pre-charging x x x x x 1 0 x fast-charging x x x x x 1 1 x taper-charging bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 charging status x x x x x x x 1 charger is enabled table 15 ? battery status register b ? 8-bit (address: 37h) ? volatile (read only) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fault output 1 x x x x x x x battery missing x 1 x x x x x x charging error x x 1 x x x x x battery over-voltage condition x x x 1 x x x x charger over-voltage condition x x x x 1 x x x charger under-voltage condition x x x x x 1 x x over-temperature alarm x x x x x x 1 x under-temperature alarm x x x x x x x 1 termination detect current threshold has been hit note 7: never write to reserved bits. configuration status registers smb135 summit microelectronics, inc 2106 3.1 11/4/2008 31 table 16 - the default device ordering number is smb135e-47 0v. it is programmed with the register contents as shown above and guaranteed over the industrial temperature range. the ordering number is derived from the customer supplied hex file. new device suffix number s (nnn) are assigned to non-default requirements. default register settings are shown in the register tables 3 through 15 as bold . default configuration register settings ? smb135e-470 v register content register content register content register content r00 f6 r04 e4 r08 80 r0c 01 r01 00 r05 0f r09 00 r0d e1 r02 0a r06 00 r0a 00 r0e 01 r03 f0 r07 01 r0b c8 r0f 80 smb135 summit microelectronics, inc 2106 3.1 11/4/2008 32 15-ball ultra csp tm package drawing smb135 summit microelectronics, inc 2106 3.1 11/4/2008 33 package drawing ( cont. ) smb135 summit microelectronics, inc 2106 3.1 11/4/2008 34 smb135 e package e = 15-ball ultra csp tm n = 32-pad qfn summit part number specific requirements are contained in the suffix (table 16) nnn part number suffix v lead free l = rohs compliant qfn package v = rohs compliant csp package 135vss 01ayww ball a1 identifier summit part number date code (yww) drawing not to scale x is the sequential number per wafer (1 for first wafer, 2 for second wafer, etc.) multiple lot designator status tracking code (summit use) lead-free (csp) notice note 1 ? this is a data sheet that describes a summit that is in production. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelec tronics, inc. assumes no responsibility for the use of any circuits described herei n, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and sche dules contained herein reflect representative operating parameters, and may vary dependi ng upon a user?s specific application. while the information i n this publication has been carefully checked, summit microelectronics, inc. shall not be li able for any damages arising as a result of any error or o mission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expe cted to cause any failure of either system or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless su mmit microelectronics, inc. receives written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimi zed; (b) the user assumes all such ri sks; and (c) potential liability of summit mic roelectronics, inc. is adequately protected under the circumstances. revision 3.1 ? this document supersedes all previous versions . please check the summit microelectronics inc. web site at www.summitmicro.com for data sheet updates. ? copyright 2006 summit microelectronics, inc. programmable power for a green planet? i 2 c is a trademark of philips corporation part marking ordering information note: subject to change at any time during production |
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